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Magazine Name : Ieee Transactions On Very Large Scale Intergration (Vlsi) Systems

Year : 2000 Volume number : 08 Issue: 06

System Level Interconnect Prediction. (Article)
Subject:
Author: A. B Kahng      D Stroobandt     
page:      637 - 638
The Interpretation And Application Of Rent'S Rule. (Article)
Subject: Analysis , Clustering
Author: D Stoobandt      P Christile     
page:      639 - 648
Prediction Of Net-Length Distribution For Global Interconnects In A Heterogeneous System-On-A Chip. (Article)
Subject: Global Interconnect , System-On-A-Chip
Author: P Zarkesh-Ha      J. A Davis      J. D Meindl     
page:      649 - 659
Heterogeneous Architecture Models For Interconnect-Motivated System Design. (Article)
Subject: Architecture Modeling , Wire-Demand Prediction
Author: D. S Wills      T. M Taha      S. M Chai     
page:      660 - 670
System-Level Performance Evaluation Of Three-Dimensional Integrated Circuit. (Article)
Subject: Critical-Path , Performance
Author: A Rahman      R Reif     
page:      671 - 678
Rent Exponent Prediction Methods. (Article)
Subject: Analysis , Clustering
Author: P Christie     
page:      679 - 688
A Compact Physical Via Blockage Model. (Article)
Subject: Analysis , System-Level
Author: Q Chen      J. A Davis      P Zarkesh-Ha     
page:      689 - 692
Using Dynamic Cache Management Techniques To Reduce Energy In General Purpose Processors. (Article)
Subject: Low-Power-Design , Memory
Author: N. E Bellas      C. D Polychronopoulos      I. N Hajj     
page:      693 - 708
The Design Of The Mgap-2: A Micro-Grained Massively Parallel Array. (Article)
Subject: Asic Systems , Fine-Grain Processing
Author: E. S Gayles      T. P Kelliher      R. M Owens     
page:      709 - 716
Intrinsic Leakage In Deep Submicron Cmosic Ics- Measurement-Based Test Solution. (Article)
Subject:
Author: C. F Hawkins      A Keshavarzi     
page:      717 - 723
Highly Regular, Modular, And Cascadable Design Of Cellular Automata-Based Pattern Classifier. (Article)
Subject: Cellular Automata , Very Large Scale Integration (Vlsi) Circuit
Author: S Chattopadhyay      S Adhikari      S Sengupta     
page:      724 - 735
Improving Path Delay Testability Of Sequential Circuits. (Article)
Subject: Delay Testing , Design For Testability
Author: T. J Chakraborty      V. D Agrawal      M. L Bushnell     
page:      736 - 740
Design Of A Configurable Accelerator For Moment Computation. (Article)
Subject: Hardware Accelaration , Image Analysis
Author: D. L Hung      S Sengkhamyong      H. D Cheng     
page:      741 - 746
Cabind: A Ga Approach To Allocation And Binding For The High-Level Synthesis Of Data Paths. (Article)
Subject: Allocation , Data Path Synthesis
Author: C Mandal      S Ghose      P. P Chakrabarti     
page:      747 - 749
Partitioning Algorithm To Enhance Pseudoexhaustive Testing Of Digital Vlsi Circuits. (Article)
Subject: Digital Vlsi Circuits , Primary Input Cones And Fanout (Rifan)
Author: B Shaer      D Landis      S. A Al-Arian     
page:      750 - 754